module Bit (input in, load, clk,output out
);reg d;assign out = d;always@(posedge clk)beginif(load)begin
d = in;endendendmodulemodule Register (input[15:0] in,input load,clk
output[15:0] out
);
Bit U0(in[0], load, clk, out[0]);
Bit U1(in[1], load, clk, out[1]);
Bit U2(in[2], load, clk, out[2]);.....
Bit U2(in[N], load, clk, out[N]);endmodule
module DMux4Way (inputwire in,inputwire[1:0] sel,output a,b,c,d
);wire w0, w1, w2, w3, nsel1, nsel2;wire[1:0] sel;
Not U0(sel[0], nsel1);
Not U1(sel[1], nsel2);
And U3(nsel1, nsel2, w0);
And U4(sel[0], nsel2, w1);
And U5(nsel1, sel[1],w2);
And U6(sel[0], sel[1],w3);
And U7(in, w0, a);
And U8(in, w1, b);
And U9(in, w2, c);
And U10(in, w3, d);endmodule